Video display terminal with automatic paging

ABSTRACT

A video display terminal is provided having a refresh memory, a character generator and a display means. The refresh memory is utilized to enable the character generator to provide signals to the display means for displaying characters. The codes of the characters are stored in the refresh memory. The refresh memory has a capacity to have stored therein a plurality of contiguous lines of characters larger than the number of lines which can be simultaneously displayed on the display. Means responsive to the refresh memory are provided for enabling the display of a selected plurality of contiguous lines of characters from the refresh memory in the display means which includes selection means for changing the selected lines from the refresh memory which are displayed in the display means.

Waited States Patent 1 3,683,359

Kleinschnitz 1 Aug. 8, 11972 [54] VKDEO DISPLAY TERMINAL WITH AUTOMATICPAGING Primary Examiner-David L. Trafton [72] lnventor: Andrew J.Kleinschnitz, Willow mwmeycaesar Bernstem Cohen Grove, Pa.

[57] ABSTRACT [73] Assignee: Delta Data Systems Corporation, I

comweus Heights, A video display terminal 18 provided having a refreshmemory, a character generator and a display means. Filed: April 30, 1971The refresh memory is utilized to enable the character [21] APPL NOJ139,064 generator to provide signals to the display means for displayingcharacters. The codes of the characters are stored in the refreshmemory. The refresh memory has [52] US. Cl. ..340/324 A, 340/1725 acapacity to havc stored therein a pluramy of com [51] Illl. Cl (7106f3/14 tiguous lines of characters larger than the number of Fleld OfSearch A lines can be simultaneously on the display. Means responsive tothe refresh memory are [56] References cued provided for enabling thedisplay of a selected plurali- UNITED STATES PATENTS ty of contiguouslines of characters from the refresh memory in the display means whichincludes selection 3,082,294 3/1963 Dean ..l 78/6.8 means for changingthe selected lines from the refresh 3,406,387 10/1968 Werme ..340/324 Amemory which are displayed i the display means 3,422,420 1/1969 Clark..340/324 A 3,614,766 10/1971 Kievit ..340/324 A 10 Claims, 11 DrawingFigures DELETE PATH (OAITROL EDIT (OUTFOL CoMT/POL CONTROL TIM/N CONTROLVIDEO DISPZA Y (oMPl/ PATENTEDAuc a 1912 SHEET 1 [IF 5 INVENTOR I w W Wm J J m. R w W ATTORNEYS- characters, the codes of which are stored inthe refresh memory. These refresh memories usually require a memorystorage location for each possible display character located on thedisplay screen. A substantial portion of the messages which are storedin the refresh memories and displayed on the display do not require fulllines of the display surface and, thus, waste positions in the refreshmemory. For example, it is common to see display presentations'which use(50 percent) or less of the available memory locations of the refreshmemory.

Systems have been provided which allow the use of a smaller memory forthe typical application wherein smaller percentages of the displaysurface are used. In these video display terminals, the refresh memoryutilizes characters to indicate the end of the line. Thus, each time thecharacter representative of the end of the line is reached, a new lineis begun on the display. A failing of these systems is, however, thatthey are limited in flexibility because they cannot utilize all of theavailable memory positions after the message has been placed within therefresh memory. Thus, if a message stored in the refresh memory is shortenough that it does not fill the entire refresh memory but does use alllines of the display, the unused portion of the refresh memory cannot beutilized since the display capability cannot be expanded to displaymessages stored in the unused portion of the memory.

It is, therefore, an object of the invention 'to overcome theaforementioned disadvantages.

Another object of the invention is to provide a ne and improved videodisplay terminal which utilizes a refresh memory with maximum storagecapability for the amount of information to be displayed.

Another object of the invention is to provide a new and improved videodisplay terminal which utilizes a unique organization of the data in therefresh memory to maximize storage capability and flexibility.

Another object of the invention is to provide a new and improved videodisplay terminal which utilizes a refresh memory which enables thestorage of more data in the refresh memory than can be displayed at onetime on a display screen and means for selectively displaying portionsof the data so that all of the data can 7 the character generator toprovide signals to the display means for displaying characters, thecodes of which are stored in the refresh memory. The refresh memory has'stored therein a plurality of contiguous lines of characters larger thanthe number of lines which can be simultaneously placed on the display.Means are provided which are responsive to the refresh memory forenabling the display of a selected plurality of contiguous lines ofcharacters from the refresh memory in the display means. The meansresponsive include selection means for changing the selected lines fromthe refresh memory which are displayed in the display means.

Other objects and many of the attendant advantages of this inventionwill be readily appreciated as the same becomes better understood byreference to the following detailed description when considered inconnection with the accompanying drawings wherein:

FIG. 1 is a schematic block diagram of a video display terminalembodying the invention;

FIG. 2 is a diagrammatic representation of the organization of thecontents of the refresh memory;

FIG. 3 is a diagrammatic representation of the paging commands;

FIG. 4 is a diagrammatic representation of the selection of lines in therefresh memory which are displayed on the video display;

FIG. 5 is a schematic block diagram of a flip-flop which is usedthroughout the system;

FIG. 6 is a schematic block diagram of the logic circuitry used toexecute a page start instruction;

FIG. 7 is a schematic block diagram of the logic circuitry utilized toexecute a form feed instruction;

FIG. 8 is a schematic block diagram of the logic circuitry utilized toexecute a page up instruction;

FIG. 9 is a schematic block diagram of a portion of the circuitry whichis used in conjunction with a page down or page end instruction;

FIG. 10 is a schematic block diagram of the remaining logic circuitryused to execute a page down instruction; and

FIG. 11 is a schematic block diagram of the remaining logic circuitryused to execute a page end instruction.

Referring now in greater detail to the various figures of the drawingswherein like reference numerals refer to like parts, a video displayterminal embodying the invention is shown in FIG. 1.

Basically, the video display terminal includes a keyboard 20, a dataregister 22, an input-output (I/O) control 24, a paging control 26, anedit control 28, a character decoder 30, a path selection control 32, arefresh memory (R.M.) 34, four registers 36, 38, 40 and 42, a linebuffer 44, a character generator 46, a video display 48, a timingcontrol 50 and horizontal and vertical drivers 52 and 54. The keyboard20 is connected to data register 22 via party line 56. The video displayterminal is also connected to a computer via the party lines 56 viaincoming and outgoing lines 58.

Four groups of gates 60, 62, 64 and 66 are also provided. As willhereinafter be seen, the gates 60, 62 and 64 provide three return orrecirculation paths to the refresh memory 34 and gates 66 enable aninput path to the refresh memory from the data register. Data register22 is connected via output lines 68 to a first input of each of gates66. It should be noted that gates 60, 62, 64 and 66 as shown in FIG. 1each represent a plurality of AND gates equal to the number of parallelbits in the refresh memory 34. This is, the refresh memory 34 preferablyincludes 7 bits in each stage thereof. Thus, a 7 bit binary codedrepresentation of a character is shifted in parallel through the refreshmemory 34. The characters are stored serially in the refresh memory.

The data register 22 also includes a plurality of input lines 70 whichare connected to the output lines of register 40. Data register 22 isalso connected via lines 72 to input-output control 24. The input-outputcontrol 24 is connected via lines 73 to the edit control 28 and pagingcontrol 26. Also connected to the edit control 28 and paging control 26s character decoder 30 which is connected thereto via lines 74. Pagingcontrol 26 and edit control 28 are connected via lines 76 and 78,respectively, to the path select control 32.

The path select control 32 includes four output lines which are labeled,respectively, in FIG. 1, DELETE, NORMAL, lNSERT" and ENTER. The deleteline 80 is connected to each of the AND gates 60 which form a deletepath for the return of characters to the refresh memory. The normal line82 is connected to each of the AND gates 62 to form a normal returnpath. The insert line 84 is connected to each of the AND gates 64 toform an insert return path and the enter line 86 is connected to each ofthe gates 66.

The outputs of each of the AND gates 60, 62, 64 and 66 are connected inmultiple via input lines 88 to the refresh memory 34. The output linesof the refresh memory 34 are connected to the register 36 via lines 90.Register 36 is connected via output lines 92 to register 38. Register 38is connected via lines 94 to register 40. Register 40 is connected viaoutput lines 96 to register 42 and register 42 is connected via outputlines 98 to AND gates 64. That is, each of the output lines of theregister 42 is connected to a different one of the AND gates 64.

The output lines 92 of register 36 are connected via lines 100 to thecharacter decoder 30. The output lines 94 of register 38 are connectedvia lines 102 to character decoder 30 and to'AND gates 60 via lines 104.In addition, output lines 94 of register 38 are connected via lines 106to line buffer 44. The output lines 96 of register 40 are connected toAND gates 62 via lines 108 and. to character decoder 30 via lines 110.The output lines 112 of line buffer 44 are connected to charactergenerator 46 and to the input of the line buffer 44 via lines 114.

Character generator 46 is connected via output line 116 to the videodisplay 48. Timing control 50 is connected to the refresh memory 34 andeach of registers 36, 38, 40 and 42 via lines 118. The timing control 50provides shift pulses on lines 118 which are provided to the refreshmemory and registers 36 through 42 to synchronously shift the data fromthe refresh memory 34 through the registers 36 through 42.

Each of the registers 36 through 42 are similar to one stage of therefresh memory 34. That is, each of the registers 36 through 42 is 7bits long and, thus, equal to the number of bits in each stage of therefresh memory. Timing control 50 is also connected via lines 120 toline buffer 44, to character generator 46 via lines 122, to thehorizontal driver 52 via lines 124 and the vertical driver 54 via lines126. The horizontal driver 52 is in turn connected to the video display48 via line 128 and vertical driver 54 is connected via lines 130 to thevideo display 48.

In operation, data can be provided to be displayed on the video display48 via either the keyboard 20 or the computer. The data is provided viathe party line 56 to the data register 22 which is in turn provided viathe AND gates 66 to the refresh memory 34. The refresh memory comprisesthe refresh memory register 34 and registers 36, 38, 40 and 42. Therefresh memory is connected serially to registers 36, 38 40 and 42 vialines 90, 92, 94 and 96.

The recirculation of the data into the refresh memory register 34normally takes place after a character has been shifted through register40 and then through gates 62 to the input lines 88 of the refresh memory34. That is, the normal line 82 from the path selection control 32 isnormally enabled to cause the enabling of gates 62 to pass thecharacters via lines 108 to the refresh memory 88. In addition, thecharacters are provided via register 38 to the line buffer 44 via lines106.

The line buffer 44 has placed therein one line of characters stored inthe refresh memory at a time. That is, each line represents a line ofcharacters that is displayed on the video display 48. Thus, if a row offorty characters is displayable on video display 48, line buffer 44includes 40 stages each having located therein a plurality of bits equalto the number of coded binary bits representative of a character. In thepreferred embodiment, there are 7 bits per stage.

The line buffer 44 is used to address the character generator 46 incombination with the signals provided on line 122 from timing control50. The video display 48 is preferably of the scan raster type so thatthe characters in line buffer 44 are constantly recirculated via lines112 and 114 through the line buffer until the number of scan linesutilized in the video display for each line of characters has progressedthrough the video display 48.

Video display 40 preferably comprises a cathode ray tube video displaywhich is controlled by the horizontal and vertical drivers 52 and 54.The timing control signals on lines and 122 from the timing control areso synchronized with the horizontal and vertical drivers 52 and 54 thatthe signals on line 116 drive the video display to provide a numericalor alphabetical representation of the characters stored in refreshmemory 34 and line buffer 44.

Registers 36, 38, 40 and 42 are utilized in conjunction with theinput-output control 24, paging control 26, edit control 28 and pathselect control 32 to enable revision or editing of the charactersdisplayed on the video display 48.

The organization or manner in which the characters are stored in therefresh memory 34 is best understood in connection with FIG. 2. FIG. 2is a diagrammatic representation of the organization of characters inthe refresh memory 34. Thus, as shown in H6. 2, the refresh memory 34 isa recirculating memory as indicated by the feed-back loop 132. As thetop of the refresh memory 34 is a control character which is indicatedby the abbreviation STX which represents the start of the text in therefresh memory 34. A second control character identified by the lettersETX represents the end of text character. Thus, the beginning of thememory is indicated by the start of text character STX) and the lastusable character in the memory is indicated by the end of text character(ETX).

It should, therefore, be noted that even though the refresh memory 34has a fixed length, the length of a display message can be variable andis effectively fixed or limited by the characters STX and E'IX whichdefine the outer limits of the usable display characters. The thirdcontrol character of importance is indicated by the letters CR whichrepresent a carriage return character and which are provided at the endof each of the contiguous lines of display data stored in the refreshmemory.

In FIG. 2, each dash represents a character which is to be displayed ona given line of the video display 48. Thus, it can be seen that aplurality of dashes are provided between the uppermost character CR andthe character STX. The carriage return character is, thus, used toindicate the end of each display line. It should also be noted that thefirst character of the second line of display is the memory location ofthe refresh memory immediately following the carriage return characteror end of line for the previous line of display.

Because only the number of characters actually displayed on the line ofthe video display are stored in the refresh memory 34, maximumutilization of the refresh memory 34 storage space is achieved. That is,assuming that forty characters can be stored on a line of the videodisplay, and it is desired that on a given line of the display only tencharacters are needed, it can be seen that there is a saving of at least28 character storage spaces in the refresh memory on the first linealone since only the STX and CR characters are required in addition tothe characters which are to be displayed on the line.

With the organization of the memory indicated herein, the data in therefresh memory may represent a large number of lines of displayableinformation. For example, if the refresh memory is approximately 3,000characters in length and the average number of characters on a displayline is 20, the data in the refresh memory can represent 150 lines ofdisplayed information.

Because of practical limitations of display systems and especially thatof the cathode ray tube type, 150 lines of displayed information cannotbe presented simultaneously. Moreover, it is not desirable to presentthis many lines of information to an operator at one time.

Thus, since the memory is capable of storing more lines of informationthan can be presented at one time on the video display 48, it is,therefore, necessary to have a means of selecting a portion of thedisplay representation in the refresh memory. Accordingly, a controlcharacter which indicates start of display (SOD) is used. The SODcharacter is used to indicate where the first character to be displayedon the first line of the video display is located in the refresh memory.Thus, in order to change the selection of which lines of displayinformation are to be presented on the video display, it is necessary tomove the start of display character (SOD) to a location other than thatof its present location in the refresh memory.

As indicated in FIG. 2, since the preferred embodiment of the videodisplay 48 can simultaneously display 27 lines of characters, the SODcharacter in refresh memory 34 is provided directly in front of the 27lines of characters in the refresh memory 34 which are displayed on thescreen. Thus, 27 carriage returns are located within the bracket whichindicates which of the lines is displayed on the screen as indicated inFIG. 2.

Thus, there are two important items of note with respect to thediagrammatic representation of FIG. 2. First, it can be seen that all ofthe characters outside of the STX and ETX characters are completelyignored by the display system. That is, the characters after the ETXcharacter and before the STX character cannot be shown or displayed onthe screen of the display 48. Next, since the number of lines displayedon the screens can be shorter than the number of lines stored in therefresh memory 34 at a time, only the number of lines which can bedisplayed on the screen are displayed directly after the recognition ofthe SOD character in the refresh memory 34.

As set forth above, since the refresh memory is capable of storing morelines of information than can be displayed atone time on the videodisplay 48, it is necessary to have a means of selecting which portionof the display representation in the memory is presented on the videodisplay. The SOD character is used to indicate where the first characterto be displayed on the first line of the video display is located in therefresh memory. Thus, in order to change the selection of which lines ofdisplay information are to be presented on the video display, it isnecessary to move the start of display character (SOD) to a point otherthan its present position in the memory.

To accomplish the movement of the SOD character, the following commandsare issued by pressing the appropriate keys provided on the keyboard 20:

1. Page start 2. Form feed 3. Page end 4. Page up 5. Page down FIG. 3 isa diagrammatic representation which is provided to aid in visualizingthe operations which are executed by the aforementioned commands. InFIG. 3, each of the rectangular boxes 134, 136, 138 and 140 which areshaded therein represent a window through which data represented in therefresh memory is viewed. This can also be understood in connection withFIG. 4 wherein a document 142 is provided having a plurality of lines144 thereon of textual material. A window 146 which is represented indotted lines is provided through which only 27 lines of data can beseen. The shaded rectangles 134 through 140 in FIG. 3 are represented bythe window 146 shown in FIG. 4. It should be understood that if thedocument 142 is moved up or down behind the window 146 all of the datain the text represented on the document can be scanned. Since the windowis considered to be stationary and the page movable, when the printedpage or document 142 is moved up one line, this is defined herein as apage up operation. When the printed page 142 is moved down one line pastthe window 146, this is defined as a page down operation.

The three other commands, page start, form feed and page end arecommands which when executed provide a very simple way for an operatorto make large jumps in the positioning of the page behind the window.Referring to FIG. 3, it can be seen that the page start command isdefined as moving the page to a point where the first character of thefirst line of the page is displayed in the first character space of thefirst line of the video display. Thus, as seen in FIG. 3, the page startdefinition requires that the SOD character be moved to the positiondirectly following the character STX.

The page end command is defined as moving the page to the point wherethe last line of information in the refresh memory is displayed on thelast line of the video display. Accordingly, as indicated by rectangle140, in order to execute a page end command, the SOD is so positionedthat the ETX character is on the last line of the display. In thisrespect, it should be noted that the ETX character is displayed on thevideo display as two vertical lines The form feed command is utilized topresent only a single message on the video display 48 at a time. Thatis, in addition to the aforementioned characters STX, CR, SOD and ETX,an end of message character (EOM) can be placed at the end of a singlemessage of data which is stored within the refresh memory. Thus, thedisplay presents only the data between the character SOD and thecharacter EOM on the video display. The end of message character EOM,thus, can be placed throughout the refresh memory at the end of eachgroup of lines which are to be displayed simultaneously as a singlemessage.

Therefore, after a first message is displayed, a form feed commandcauses the characters after the EOM character (1 in FIG. 3), which waslast displayed, to be displayed next. The form feed command, thus,causes the start of display character SOD to be moved to the pointfollowing the next end of message character that is encountered in therefresh memory. Thus, as indicated in the FIG. 3, the window representedby rectangle 136 is moved to the position shown by rectangle 138 whichdirectly follows the EOM character. Thus, in a form feed command, theSOD character is moved to the character position after the EOMcharacter.

Referring back to FIG. 1, all data and commands enter the video displayterminal in the form of coded characters of 7 bits each. Each characteris entered into the data register 22 and the input-output control 24 isprovided to decode the character and recognize whether it is data to beentered in the refresh memory 34 or a control character.

When data is to be entered, the input-output control 24 provides theproper signal to the edit control 28 where all entries of data into thememory are controlled. When it is determined that the character providedin data register 22 is a control character, the input-output control 24provides the proper signals to either the edit control or the pagingcontrol in accordance with the type of command issued to the inputoutputcontrol 24.

The edit control and paging control provide the proper logic signals tothe path selection logic in the path selection control 32 which controlthe gates 60 through 66 which form a portion of the recirculating loopof the refresh memory 34. The control of the gates 60 through 66 enablesthe insertion and deletion of the data character within the memory aswell as the replacement of data characters with new data characters andthe movement of control characters within the refresh memory.

As set forth above, the refresh memory 34 preferred in the instantembodiment is a recirculating memory. As set forth above, each characterin the refresh memory 34 passes through the registers 36, 38, 40 and 42which enable the editing of the characters in the refresh memory. Theregisters 36 through 42 enable four types of operation which aresubsteps in the paging command previously referred to. Normal operationis caused by an enabling signal on the normal line 82 from the pathselection control to gate 62 which enables the characters in the refreshmemory to be routed via the registers 36, 38 and 40 to the refreshmemory 34. Normal operation is utilized where the characters in therefresh memory are constantly being displayed on the screen of the videodisplay 48.

A first operation called delete enables the removal of a character fromthe refresh memory without leaving a space between the previouslypreceding and following characters. This function, thus, closes up thedata from the previous organization. This operation of deletion isperformed by detecting when a character to be removed is at register 40.For example, when a control character such as SOD is to be removed fromthe refresh memory and the SOD character is in register 40, thecharacter decoder 30 detects this condition and provides signals to theedit and page control which, in turn, provide signals to the path selectcontrol which cause the normal line 82 to be be de-energized and thedelete line to be enabled. Thus, the character that is in register 40 isnot re-entered into the refresh memory 34 and the character that is inregister 38 immediately follows into the refresh memory the characterthat was ahead of the character in register 40 and which is presently inregister 42.

Since gates 62 and 64 are disabled, the character in register 38 isplaced directly into the last position of the refresh memory 34. Thedelete line 80 stays enabled until the ETX character indicating the endof the text reaches register 40 at which time the delete line 80 isdisabled and the normal line 82 is enabled. This opera tion has theeffect of providing an extra memory position after the ETX characterwhich maintains the same number of positions in the refresh memory 34 aswere provided previous to the delete operation. However, it should benoted that the data from one location has been removed and the remainingdata closed up at that location.

The insert operation is performed in a similar manner. The insertoperation requires the separation of existing data in the refresh memoryand inserting a data character or control character in the positionwhere the existing data has been separated.

in order to execute the insert operation, when a character after whichit is desired to insert a new character has been entered into therefresh memory from register 40, at the next clock time the data isshifted in the registers so that the character following the one justentered into the refresh memory is located in register 40. The characterto be inserted is presently located in the data register 22. The normalpath via gates 62 is then disabled and the enter line 82 is enabled forentering data through gates 66 during the next clock time or shift pulseinto the refresh memory.

The enabling of gates 64 and the disabling of gates 62 causes thecharacter in register 40 to be inserted only into register 42 and notinto the refresh memory. At the same time that the character in registeris shifted into register 42, the enter line 86 is pulsed to enable gate66 to pass the character in data register 22 via line 68 to input lines88 of the refresh memory 34.

Where it is desired only to insert a space between two characters, theenter line 86 is not enabled and accordingly a blank character is placedinto the refresh memory 88. Until the ETX character is detected inregister 40, the normal line 82 remains disabled and the insert line 84remains enabled. As soon as the ETX character is provided via register42 to the refresh memory 34, the insert line 84 is disabled and normalline 82 enabled again. Thus, a character is effectively deleted from theunused portion of the refresh memory after the ETX character.

It should be noted that for each pass through the recirculating refreshmemory, only one character can be inserted or deleted in the displayablearea of the refresh memory. It is possible to perform more complicatedediting functions such as the clearing of the whole line by issuing asingle command by doing the delete operation repetitively until all ofthe characters on that line have been removed. Moreover, an entire linecan be inserted between two lines by inserting between a carriage returnand the next character in the refresh memory an additional carriagereturn character.

It shouldalso be noted that the characters in the refresh memory whichare displayed on the video display are provided via register 38 to lines106 which are connected to the line bufier 44. Thus, the editing of therefresh memory is not seen on the video display until a completerecirculation of the characters in the refresh memory 34.

The timing control recirculates the refresh memory 34 for each completescan on the video display 48. Thus, after the last line has beendisplayed on the video display 48, the timing control 50 provides shiftpulses on line 118 which cause the refresh memory to be shifted so thatduring the retrace time, the refresh memory is shifted around until theSOD character and each of the data characters provided on the first lineare stored in the line buffer 44.

Thus, during the first line of the scan raster, each of the characterswhich are provided on the first line of the video display are located inthe line buffer 44. After the line of characters has been displayed onthe video display, the timing control again shifts the refresh memory 34and registers 36 through 42 so that each of the characters after thefirst carriage return are pro vided in the line buffer 44. The secondline of characters is then displayed on the video display 48.

It should be understood that the carriage return character indicates theend of the line and, thus, after a carriageretum is detected in register38, blank spaces are provided to the line buffer 44 until the charactersprovided on the second line are shifted to the initial positions in linebuffer 44 representative of the start of a line on the video display 48.This process continues until the last line displayed on the videodisplay has been provided in the line buffer 44. The timing control thenprovides pulses on shift pulse line 118 to the refresh memory andregisters 36 through 42 to cause the first line of data to be readied tobe entered into the line buffer prior to the first scan line on thevideo display 48.

The paging control operations are basically comprised of the insert anddelete operations. However, the function is to move the start of thedisplay character to a new location within the displayable portion ofthe memory. That is, the portion of the memory between the ST'X and ETXcharacters is the displayable portion of the memory. As will hereinafterbe seen, the movement of the start of display character is accomplishedby first deleting the start of display character from its presentlocation and inserting the start of display character in a new locationwhich is determined by the logic of the paging control at a locationdepending upon the type of command which is issued.

As described above, the delete operation is performed by switching fromthe normal path to the delete path. Thus, where the start of displaycharacter SOD is to be deleted from the register, when the character isin the register 40, but before it has been entered into the memory, thepath is switched from the normal path to the delete path. All charactersfollowing the SOD character are then entered into the refresh memoryfrom register 38 until such time as the logic determines that it isdesired to reinsert the start of display character into the refreshmemory.

The insertion of the start of display character is performed when thepaging control determines that the start of display character should beinserted between the characters which are in registers 36 and 38. Thecharacter ,is register 38 is loaded into the refresh memory through thedelete path provided by AND gate 60. The same character is also shiftedinto register 40 and the character is register 36 is shifted intoregister 38. The code for the start of display character is then enteredinto register 40. The recirculating path is returned to the normal statebefore the next character is loaded into the memory. The character thenloaded into the refresh memory is the start of display character SODwhich is now in register 40 and takes its position in the refresh memorybetween the proper characters. This operation will be more completelyunderstood in connection with the logic circuitry diagrams of the pagingcontrol utilized for the paging operations.

In FIG. 5, a block diagram is shown of a flip-flop that is usedthroughout the system. Flip-flop shown in FIG. 5 is known as a D-typeflip-flop which is conventional in the data processing area, computerarea and other areas of the digital electronics industry. The flipflop150 includes a D input line 152, a clock (CLK) input line 154, a reset(R) input line 1 56, a set (S) input line 158, a Q output line and a Qoutput line 162. The operation of the flip-flop is such that when asignal is provided on the clock input 154 which changes from a negativeto a positive signal, the leading edge of the signal causes a triggeringof the state of the flip-flop 150 which causes the signal on the Qoutput line 160 of the flip-flop 150 to assume the same logic state asthat applied to the D input line 152 of the flip-flop. It should benoted that this happens irrespective of the previous state of theflip-flop so that if the flip-fiop 150 was in the set state and a 1input were provided to the D input 152, the Q output 160 would remain ata 1 input even though a clock pulse or leading edge were received at theclock input 154 of the flip-flop 150.

Similarly, if the leading edge signal on the clock input line 154 werereceived when the D input line 152 had a input thereto, the Q outputline 160 would have generated therein a 0 output. The set input line 158is a direct set line and overrides the clock input 154. Thus, if theflip-flop 150 is in the 0 state, a l or enabling signal on the set inputline 158 causes the flip-flop to be set and the Q output line 160 to beat the 1 state. Similarly, a reset input line 156 overrides a clockinput 154 and, thus a 1 on the reset input line 156 causes a reset ofthe flip-flop 150 and the consequent output signal on the Q output 162to go to a l state and the output signal on the Q output 160 to go to a0 state.

Referring now to FIG. 6, the logic circuitry to execute the page startcommand is shown therein. Basically, the logic circuitry in the pagingcontrol 26 which executes the page start command comprises a pair offlip-flops 200 and 202 and three AND gates 204, 206 and 208. AND gate204 includes a first input line 210 which receives a page start signal(PST) from the inputoutput control 24 when a control character isrecognized in the data register 22 indicative of a page start characterbeing inserted into the data register from the keyboard or the computer.

The other inpgt to AND gate 204 is connected via line 212 to the Qoutput line of flip-flop 200. Output line 214 of gate 204 is connectedto the D input line of flip-flop 200. The Q output line of the flip-flop200 is connected to a line 216 and to a first input line 218 of AND gate206. Line 216 is connected to the path select control and causes adelete instruction t be provided from the paging control 26 via lines 76to the path selection control 32. The Q output line of flip flop 200 isalso connected to the clock input line 220 of flip-flop 202. A true orpositive signal (+V) is connected to the D input line of flip-flop 202.Line 222 which is connected to the reset input of flip-flop 202 receivesa page complete signal (PG COMP) at the end of a page start commandwhich indicates the operation has been completed.

The Q output line 224 of flip-flop 202 is connected to a first inputline of AND gate 208. The second input line 226 receives an enablingsignal upon the detection of the SOD character in register 40 by thecharacter decoder 30. Similarly, the clock input line 228 of flipflop200 also receives the signal from character decoder 30 that an SODcharacter has been detected in register 40.

The second input line 230 of AND gate 206 receives an enabling signalfrom the character decoder 30 when the STX character is recognized atregister 40. As indicated in FIG. 6, where the numeral appears aftereither the character SOD or STX, it indicates that the character SOD orSTX is recognized at register 40 by the character decoder 30. The samenomenclature is used hereinafter with respect to registers 36 and 38.The AND gate 206 provides an enabling signal on output line 232 when anSTX 40 signal is received on line 230 and the flip-flop 200 is in theset state causing the high signal on input line 218.

The output of AND gate 206 when it is enabled is utilized to provide asignal on line 232 indicative of the fact that the page start logicshould receive a signal indicative of a start of display at register 40signal. That is, the legend in FIG. 6, PG SOD 40 indicates that thelogic in FIG. 6 which is to receive the SOD 40 signal when the SOD 40character is recognized in the register 40, should also receive enablingsignals when AND gate 206 is enabled. Thus, an enabling signal is againprovided on line 228 and line 226 to the clock input of flip-flop 200and the AND gate 208, respectively. The output of AND gate 208 isconnected to line 234 which receives a high signal when AND gate 208 isenabled by the signals on lines 224 and 226. The output line 234 ishardwired to register 40 to provide the SOD character in register 40when AND gate 208 is enabled.

It can be seen that the operations to be performed by a page startcommand are to locate the start of display character, delete thischaracter from the refresh memory, locate the start of text and insertthe start of display character after the start of text character. Thus,when the page start command (PST) is received from the input-outputcontrol 24, it is applied to AND gate 204. Assuming that a previous pagestart command had been completed, the flip-flop 200 is in the resetstate thereby causing line 212 from the Q output thereof to be enabled.Thus, gate 204 is enabled by the PST signal causing the line 214 toreceive an enabling signal.

As soon as the SOD character is located in register 40, the characterdecoder 30 recognizes this condition and provides an enabling signal onthe clock input line 228 to flip-flop 200 which causes flip-flop 200 tobe set and thereby provide an enabling signal on line 216 to the pathselect control 32 which causes a deletion of the SOD character inregister 40.

Referring back to FIG. 1, it will be remembered that the deleteinstruction causes the normal line 82 to be disabled and the delete lineto be enabled. Thus, the SOD character in register 40 is deleted fromthe data in the refresh memory 34. The delete line 80 remains enableduntil such time as the start of text character is received in register40.

As soon as the STX character is in register 40, it is recognized by thecharacter decoder 30 and provided to the paging control 26, AND gate 206is enabled since the flip-flop 200 remains in the set condition. Theoutput signal on line 232 is applied to both flip-flops 200 and AND gate208 via lines 228 and 226. The signal on line 228 causes the flip-flop200 to be reset as a result of the fact that the D input line 214 offlip-flop 200 has applied thereto a disabling signal. That is, as soonas flip-flop 200 is set, the Q output line 212 goes low causing the gate204 to be disabled. Accordingly, upon receipt of the leading edge of theSOD 40 signal, the flip-flop 200 is reset.

When flip-flop 200 is reset, the signal on line 220 goes high therebycausing a leading edge to be applied to the clock input of flip-flop202. Flip-flop 202 having the true signal at the D input thereof is setthereby causing the output line 224 to receive an enabling signal whichcauses the enabling of AND gate 208 which has applied thereto the signalfrom line 232.

The enabling of gate 208 causes an enabling signal on line 234 whichcauses the code of the SOD character to be inserted in register 40. Thesignal on line 234 is also applied to a suitable delay and then providedon line 222 to indicate that the page start operation has beencompleted. That is, the suitably delayed SOD 40 signal is used tocomplete the operation of the page start command and is provided on line222 to reset flip-flop 202. Since both flip-flops 200 and 202 are in thereset condition, the circuitry is in the initial condition which enablesthe receipt of another page start command and the, execution thereof.The PG COMP signal provided to line 222 is also provided to theinput-output control 24 and causes the disabling of the PST signal.

It should be noted that when the flip-flop 200 is reset, it causes theline 216 to be disabled which causes the edit control to return the pathselection control to the normal path. That is, the delete line 80 isdisabled and normal line 82 is enabled again. Thus, the SOD characterwhich is placed in register 40 is the next character that is placed intorefresh memory 34 via gates 62. It should also be noted that prior tothe shifting of the SOD character in the refresh memory, the STXcharacter is provided to the refresh memory via the gates 60 fromregister 38 so that the SOD character follows directly after the STXcharacter in the memory.

The logic for executing the form feed command is shown in FIG. 7.Basically, it can be seen that the circuitry in FIG. 7 is substantiallyidentical to that of the circuitry in FIG. 6. The form feed logic, thus,includes a pair of flip-flops 240 and 252 and three AND gates 254, 256and 258. A first input line 260 is connected to AND gate 254 andreceives the form feed signal (FF). The second input line 262 of ANDgate 254 is connected to Q output line of fiip-fiop 250. The output line264 of AND gate 254 is connected to the D input line of flip-flop 250.

The output line of flip-flop 250 is connected to a first input line 266of AND gate 256 and to line 268 which is connected to the path selectcontrol 32 via lines 76. The second input line 270 to AND gate 256 isconnected to the output of character decoder 30 and receives a signalthereon when the end of message EOM) character is recognized in register40.

The output line 272 of AND gate 256 is connected to the clock input line274 of flip-flop 250 and the input line 276 of AND gate 258. Both theclock. input line 274 and input line 276 also receive signals thereonindicative of the receipt of the SOD character in the register 40. TheQoutput line 278 of flip-flop 250 is connected to the clock input lineof flip-flop 252. The 0 output line 280 of flip-flop 252 is connected tothe second input line of AND gate 258. The output line 282 of AND gate258 is hard-wired to the register 40 for providing the SOD character inregister 40 when the AND gate 258 is enabled. The reset line 284 offlipflop 252 receives the page complete (PG COMP) signal for the formfeed operation which is generated by the signal on line 282 of AND gate258 and is then suitably delayed.

In operation, prior to the receipt of the form feed signal, theflip-flops 250 and 252 are in the reset condi tion. The receipt of aform feed signal on line 260, thus, causes the AND gate 254 to beenabled and the flipflop 250 is then set as soon as the SOD character isrecognized in register 40. Upon the setting of flip-flop 250, the pathselect control is caused to have the normal line 82 disabled and thedelete line 80 enabled. The SOD character is removed from the refreshmemory. As soon as the EOM character is recognized at register 40, line270 is enabled thereby enabling AND gate 256 which causes the FF SOD 40signal to be generated on line 272.

The AND gate 254 which has been disabled by the setting of flipflop 250,thus, causes the flip-flop 250 to be reset as the leading edge of the FFSOD signal is provided on line 274 to flipflop 250. The resetting offlip-flop 250 causes the setting of flip-flop 252 which in turn causesthe enabling of AND gate 258. The enabling of AND gate 258 results inthe insertion of the character SOD in register 40 and also causes thedelayed PG COMP signal on line 284 to reset the flipflop 252 therebyending the form feed command. The PG COMP signal is also provided to theinput-output control 24 to terminate the FF signal. It can, therefore,be seen that the SOD character was removed from the refresh memory andreturned to a position following the next end of message character inthe refresh memory. It should also be noted that when flip-flop 250 isreset, the signal on line 268 causes the path selection control 32 tochange from the delete path to the normal path and thereby enables theinsertion of the SOD character directly after the EOM character in therefresh memory.

Referring now to FIG. 8, the logic for the execution of the page up (PGUP) command is shown therein. The logic for the page up command issimilar to the logic used inthe page start and fonn feed command shownin FIGS. 6 and 7, respectively. Thus, the page up logic includes a pairof flip-flops 300 and 302 and three AND gates 304, 306 and 308. Thefirst input line 310 to AND gate 304 is connected to the output of theinput-output control 24 via lines 73 and receives a page up (PG UP)signal when the page up command has been inserted into the data register22 and recognized by the input-output control 24.

The second input 312 of AND gate 304 is connected to the 6 output offlip-flop 300. The output line 314 of AND gate 304 is connected to the Dinput line of flipflop 300. The Q output line of flip-flop 300 isconnected to a first input line 316 of AND gate 306 and to line 318which is connected to the path selection control 32. The line 318, whenenabled, causes a delete operationin the path selection control.

The second input line 320 to AND gate 306 is connected from thecharacter decoder 30 which provides an enabling signal thereon when theCR character is recognized in register 40. When AND gate 306 is enabled,it provides anoutput signal on line 322 which is received on the clockinput line 324 of flip-flop 300 and input line 326 of AND gate 308. Theclock input line 324 of flip-flop 300 also receives a signal thereonwhen the SOD character is recognized in register 40 from the characterdecoder 30.

The Q output line 328 of flip-flop 300 is connected to the clock inputline of flip-flop 302. The D input line of flip-flop 302 is connected toa true signal source (+V) and the reset input line 330 receives a PGCOMP signal thereon when the page up operation is complete. The Q outputline 332 of flip-flop 302 is connected to the second input of AND gate308 which, when enabled, provides an output signal on output line 334which is connected to register 40 and is hardwired to provide an SODcharacter in register 40 when the AND gate is enabled. The output signalon line 334 is suitably delayed to provide the page complete (PG COMP)signal to line 330 and to input-output control 24 which terminates thePG UP signal.

In operation, flip-flops 300 and 302 are in the reset condition prior tothe receipt of a page up command signal on line 310. AND gate 304 isenabled by the PG UP signal and causes the setting of flip-flop 300 uponreceipt in register 40 of the SOD character. The setting of flip-flop300 causes the signal on line 318 to go high which in turn causes thepath selection control to disable the normal output line 82 and enabledelete line 80, thus, causing the removal of the SOD character from therefresh memory.

The delete line 80 remains enabled until such time as the carriagereturn character CR is recognized in register 40 by the characterdecoder 30. Thus, as soon as the next CR character is received inregister 40, the AND gate 306 is enabled thereby causing the resettingof flip-flop 300. This resetting of flip-flop 300 causes the Q outputline to go high thereby causing the setting of flip-flop 302. Thesetting of flip-flop 302 causes the enabling of gate 308 which alsoreceives the SOD 40 signal from the output line 322 of AND gate 306. TheSOD character is then set into the register 40 in place of the carriagereturn character CR which is presently located therein. Since theflip-flop 300 is reset, the delete path is disabled and the normal pathenabled causing the SOD character to be inserted on the next shift pulseinto the refresh memory 34. It should be remembered that the CRcharacter immediately preceded the SOD character into the refresh memoryon the previous shift pulse via the delete path. The SET SOD 40 signalprovided on line 334 is suitably delayed and provided to line 330 whichthereby resets flip-flop 302 and completes the page up operation.

It can, therefore, be seen that the page up operation effectivelyremoves the SOD character and provides it directly after the nextcarriage return character. This means that the page up operationefiectively causes the start of display character to be placed after thenext succeeding line of storage of data in the refresh memory 34. Itwill be remembered that a page up operation is representative of adocument being moved upwardly behind the window which represents thedisplay.

The page down and page end commands require that the start of displaycharacter be moved to a location which in the case of the page downcommand is earlier in the refresh memory than its present location. Inthe page end command, it may also be required that the start of displaycharacter be inserted in a position which is earlier in the refreshmemory than its present location. In order to accomplish thedetermination of the location at which the start of display character isto be reinserted, the circuitry which is shown in FIG. 9 is required.

The circuitry in FIG. 9 basically comprises a counter 350, a counter352, a comparator 354 and AND gates 356, 358, 360 and 362. Counter 350includes a counting (CT) input line 364 which receives counting signalsfrom AND gate 358 which step the counter 350. The counter also includesinput line 366 which is a preset (P) input line to preset the count inthe counter 350 to l. Counter 350 also includes a reset (R) input line368 which resets the counter to all zeroes when an enabling signal isprovided on line 368.

Counter 350 also includes an output line 370 which indicates whether thetotal in the counter is either positive or negative. The count in thecounter 350 is provided via lines 372 to the comparator 354. Counter 352includes a counting (CT) input line 374 which steps the counter 352 eachtime a positive signal is received thereon from AND gate 356. A reset(R) line 376 is also provided to the counter 352 which causes thecounter to be reset to all zeroes when an enabling signal is providedthereon.

A preset (P) input line 378 is also provided to counter 352 whichpresets the counter to a count of 27 when the line is enabled. Counter352 also includes an output line 380 which is used to indicate whetherthe count in counter 352 is negative or positive. The count in counter352 is provided via lines 382 to comparator354. The comparator 354, inaddition to having input lines 372 and 382, includes an output line 384which has a true or enabling signal (CTR=) generated thereon when thecount in counters 350 and 352 are equal.

The output of AND gate 356 is connected to input line 374 of the counter352. The gate 356 also includes a pair of input lines 386 and 388. Inputline 386 is connected to the character decoder 30 which provides asignal on line 386 when the carriage return character CR is located inregister 36. The line 388 is connected to the output of the page endlogic circuitry and will be discussed in greater detail hereinafter. Theoutput line of AND gate 358 is connected to the count line 364 of thecounter 350. The AND gate 358 also includes a pair of input lines 390and 392. Input line 390 is connected to the output of the characterdecoder 30 which provides an enabling signal on line 390 when thecarriage return character CR is detected in register 36. Line 392 isconnected to the output of the page down logic and will also bediscussed in greater detail hereinafter.

The output line of AND gate 360 is connected to the preset input line366 of counter 350. The AND gate 360 includes a pair of input lines 394and 396. The first input line 394 is connected to the output of thecharacter decoder 30 which provides a high signal on line 394 when theSTX character is recognized in register 36. Input line 396 to the ANDgate 360 is connected to the output of the page down circuitry. Theoutput line of AND gate 362 is connected to the preset input line 378 ofcounter 352.

The AND gate 362 includes a pair of input lines 398 and 400. Line 398 isconnected to the output of the character decoder 30 and receives anenabling signal when the character STX is located in register 36. Line400 is connected to the output of the page end circuitry.

As the refresh memory is recirculating, the counter 350 is used -tocount the number of lines starting with the start of the text characterSTX. Each time an STX is located in register 36, the AND gate 360 isenabled to preset the counter 350 to a ---1 via line 366. AND gate 360is enabled as long as a page down command is weceived by the page downcircuitry and, thus, the PGD signal is high and, thus, provides via line396 an enabling signal to AND gate 360. Therefore, since the start oftext character sets the counter to a -l, the counter 350 contains at alltimes the number which is one less than the number of lines indicated bythe number of carriage returns that have reached register 36. As therefresh memory recirculates, each carriage return character received inregister 36 causes counter 350 to be stepped as long as the PGD DELETEsignal remains high to gate 358.

As the counter 350 is used to maintain the count of the lines less onethat have passes through the register 36, counter 352 is used todetermine the location where the start of display character is to bere-entered if a page end command is requested. As set forth above, thevideo display preferably includes 27 lines of characters. Thus, since apage end instruction requires that the SOD character be inserted 27lines from the end of text (ETX) character, the counter 352 is preset to27 so that the location of where the start of display character is to beinserted is located in counter 352. That is, in order to locate properlythe position of the SOD character in a page end command, the counter 352is preset to 27 each time the start of text character STX reachesregister 36. The STX character continuously presets the counter as longas the page command signal is not received as indicated by the PGElegend adjacent line 400.

It can, therefore, be seen that during an operation other than the pagedown or page end command at the video display terminal, the two counters350 and 352 are continuously predeterrnining the number of the linewhere the start of display character is to be inserted if either ofthese commands is requested.

The page down logic used in combination with the circuitry of FIG. 9 isshown in FIG. 10. As seen therein, the page down logic comprises a pairof flip-flops 402 and 404 and four AND gates 406, 408, 410 and 412,respectively. The AND gate 406 includes a first input line 414 whichreceives the page down (PGD) signal from the input-output control 24.The second input line 416 is connected to the Q output line of flip-flop402.

The output of AND gate 406 is connected via line 418 to the D input offlip-flop 402.

The output line 420 of flip-flop 402 is connected to the path selectioncontrol 32 via line 420 and to AND gates 408 and 410 via line 422. Theenabling signal on line 420 causes the path selection control to changefrom the normal to the delete path. The setting of flip-flop 402 alsocauses line 422 to enable gates 408 and 410. The second input line ofAND gate 408 is connected to the output of the character decoder 30which provides an enabling signal on line 424 when the STX character isreceived in register 36. The second input of AND gate 410 is connectedto line 384 from FIG. 9 which is the output line of comparator 354 whichindicates that the counters 350 and 352 are equal. The output line ofAND gate 408 is connected to line 376 of counter 352 and the outputsignal provided on line 376 thereby causes the resetting of counter 352.The output line 426 of AND gate 410 provides a signal which'indicatesthat the page down command requires the SOD character be inserted inregister 38. This signal is delayed one clock time in order to beconnected to the clock input line 428 of flip-flop 402 and input line430 of AND gate 412.

The O output line 432 of flip-flop 402 is connected to the clock inputof flip-flop 404. The D input line of flip-flop 404 is connected to asource of positive voltage (+V) and the reset input line receives thepage complete (PG COMP) signal for resetting flip-flop 404.

The Q output line 436 of flip-flop 404 is connected to the other inputof gate 412. The gate 412 provides an output signal on line 438 whichcauses the setting of the SOD character in register 40. That is, line430 is also hardwired to the register 40 for providing the SOD charactertherein.

The line 438 is also connected to a suitable delay so that the signalcan be provided to line 434 of flip-flop 404 to reset flip-flop 404 whenthe page down operation has been completed and to the input-outputcontrol 24 to terminate the PGD signal.

In operation, when a page down signal is received on line 414, AND gate406 is enabled thereby causing the line 418 to have a high signalthereon so that upon receipt of the SOD character in register 40,flip-flop 402 is set. As soon as flip-flop 402 is set, the Q output line420 of flip-flop 402 causes the path selection control to be changedfrom the normal to the delete path. It should be noted that the PGDDELETE signal, which is obtained by inverting the PGD DELETE signal,provided to line 392 in FIG. 9 of AND gate 358 goes low as a result ofline 420 going high. Accordingly, no further stepping of counter 350 ispossible since the gate 358 is disabled by the low input on line 392.

Thus, the count in counter 350 indicates the line at which the SODcharacter was previously located minus one. Counter 350, thus, maintainsthe count of the lines at which the SOD character is to be inserted inorder to effect a page down command. The enabling of line 420 offlip-flop 402 also causes the AND gate 408 to be enabled when the STXcharacter is received in register 36. Thus, the receipt of the STXcharacter in register 36 causes gate 408 to be enabled and therebyresets' counter 352 to all zeroes. The counter 352 is reset to allzeroes and is stepped by each of the carriage return characters CR whichare received in register 36. Accordingly, when the count in counter 352reaches the count in counter 350, the comparator 354 indicates on line384 that the counters are equal which causes AND gate 410 in FIG. 10 tobe enabled and thereby provide an output signal on line 426 which isdelayed for one clock time and then applied to lines 428 of flip-flop402 and line 430 of AND gate 412.

The receipt of the high signal on line 428 causes the flip-flop 402 tobe reset since the AND gate 406 had been disabled previous thereto bythe low signal on the 6 output line of the flip-flop. The resetting offlip-flop 402 causes the signal on line 432 to go high thereby causingthe setting of flip-flop 404. The setting of flipflop 404 causes theenabling of AND gate 412 since the signal on line 430 has remained high.

The AND gate 412 provides an output signal on line 438 which causes theinsertion of the SOD character into register 40. The suitably delayedsignal on line 438 is then provided via line 434 to the reset input ofline 404 and resets flip-flop 404. When the PGD DELETE signal goes lowas a result of the resetting of flip-flop 402, the path selectioncontrol causes the delete path of the recirculation loop of the refreshmemory to be disabled and the normal path to be enabled.

It can, therefore, be seen that in the page down operation, the start ofdisplay character is moved one line earlier in the refresh memory thanits previous location. Accordingly, this has the effect of moving adocument down with respect to a stationary viewing window as seen inFIG. 4.

The logic used in combination with the logic of FIG. 9 for the executionof a page end command is shown in FIG. 11. The page end logic utilizesthree flip-flops 450, 452 and 454 and four AND gates 456, 458, 460 and462. The D input line 464 of flip-flop 450 is connected to the outputline of input-output control 24 which indicates the receipt of a pageend (PGE) command from the data register 22. The clock input line 466 offlip-flop 450 is connected to the output of the character decoder whichindicates the receipt of an ETX character in register 40.

Reset (R) input line 468 of flip-flop 450 receives a page complete (PGCOMP) signal which indicates the end of the operation of the page endcommand. The Q output line 470 of flip-flop 450 is connected to thefirst input of AND gate 456. I"he other input of AND gate 456 isconnected to the Q output line of flip-flop 452. The output line 472 ofAND gate 456 is connected to the D input line of flip-flop 452.

The clock input line 474 of the flip-flop 452 is connected to the outputof character decoder 30 and receives a signal thereon when the characterSOD is received in register 40. As will hereinafter be seen, line 474 isalso connected via delay means (not shown) to the output of AND gate460. The Q output line of flipflop 452 is connected via line 476 to thepath select control 32 to change the recirculation loop of the refreshmemory 34 from a normal path to a delete path and via line 478 to ANDgates 458 and 460. The Q output line 480 of flip-flop 452 is connectedto the clock input line of flip-flop 454.

A second input line 482 of AND gate 458 is connected to the characterdecoder 30 which provides a high signal on line 482 when the STXcharacter is recognized in register 36. The second input line of ANDgate 460 is connected to output line 384 of comparator 354 in FIG. 9.The output line of AND gate 458 is connected to line 368 in FIG. 9 ofcounter 350.

AND gate 460 includes an output line 484 which is utilized to indicatethat the SOD character should be located within the register 38. Thissignal is delayed one clock time and then applied to line 474 offlip-flop 452 and to an input line 486 of gate 462. The second inputline to gate 462 is connected via line 488 to the Q output line offlip-flop 454.

Gate 462 is connected via output line 490 to the register 40 and thecode for the SOD character is hardwired therein to enable the insertionof the code for the SOD character in register 40 when gate 462 isenabled. The signal on line 490 is delayed a suitable period of time forthe transient signals to be quiescent and then applied via line 492 tothe reset input of flip-flop 454. The D input of flip-flop 454 isconnected to a positive voltage source (+V).

In operation, the page end (PGE) signal being provided by theinput-output control 24 is received at the D input of flip-flop 450.Upon the receipt of the ETX character in register 40, the flip-flop 450is set. The setting of flipflop 450 causes the Q output line 492 whichis connected to line 388 in FIG. 9 to go low thereby causing thedisabling of AND gate 356 therein.

The disabling of AND gate 356 causes the count in counter 352 to befixed at the count which indicates the number of lines between STX andETX minus 27. This, of course, is the number of lines from the start oftext that the SOD character should be inserted so that a page endcommand can be executed.

The setting of flip-flop 450 also enables gate 456 which in turn causesthe line 472 to have a high signal placed thereon so that the receipt ofthe start of display character in register 40 causes the setting offlip-flop 452. The setting of flip-flop 452 causes a high signal on line476 which enables the delete operation of the SOD character by changingthe recirculating path in the refresh memory from the normal path to thedelete path.

The setting of flipflop 452 also causes the enabling of AND gate 458 and460 so that upon the receipt of the STX character in register 36, ANDgate 458 is enabled and thereby causes the resetting of counter 350.Counter 350 is then set to all zeroes and then is stepped by the receiptof CR characters in the register 36. When the count in counter 350reaches the count in counter 352, comparator 354 indicates thiscondition by generating a CTR= signal on line 384 indicating that thetwo counters have an equal count which causes AND gate 460 in FIG. 11 tobe enabled and, thus, provide an output signal on line 484 indicatingthat the SOD character should be in register 38. This signal is thendelayed one clock time and provided via line 474 to the flip-flop 452which causes the resetting of flipflop 452 as the output signal on line472 is made low by the disabling output signal on the O output offlip-flop 452 when the flip-flop 452 was set.

The resetting of flip-flop 452 causes the setting of flip-flop 454 whichin turn enables the AND gate 462. When AND gate 462 is enabled, the SODcharacter is inserted in register 40 and the signal on line 490 is thensuitably delayed and provided as a PG COMP signal via line 492 offlip-flop 454 to reset the same. The PG COMP signal is also provided vialine 468 to reset flipflop 450.

It should be noted that in each of the logic circuits which are used toexecute the various paging commands, the PG COMP signal is also providedto the input-output control 24 in FIG. 1 to terminate the generation ofthe command signals.

It can, therefore, be seen that a new and improved video displayterminal with automatic paging has been provided. The refresh memoryused in the video display terminal is a recirculating memory withintermittent clock control. The organization of the data within therefresh memory enables substantially percent) use of the refresh memorystorage capability. Moreover, the edit and page control enables theentire contents of the refresh memory to be displayed on the videodisplay.

Moreover, the paging commands are easily executed and are a verypowerful tool of the operator to have access to each portion of therefresh memory that is desired.

The keyboard of the video display terminal is also so chosen that thepage up and page down buttons may be continuously depressed until thenumber of lines up or down in the refresh memory that are desired can beaccomplished without intermittently pressing the page up or page downbuttons. The page start, form feed and page end commands accomplish avery rapid removal of the start of display character from one positionto a predetermined position in the refresh memory. These commands areaccomplished rapidly by means of the logic circuitry utilized for theexecution of each of the circuits.

Without further elaboration, the foregoing will so fully illustrate myinvention that others may, by applying current or future knowledge,readily adapt the same for use under various conditions of service.

What is claimed as the invention is:

, 1. In a video display terminal having a refresh memory, a charactergenerator and a display means wherein said refresh memory is utilized toenable said character generator to provide signals to said display meansfor displaying characters, the codes of which are stored in said refreshmemory, said refresh memory having stored therein a plurality ofcontiguous lines of characters larger than the number of lines which canbe simultaneously displayed on said display, means responsive to saidrefresh memory for enabling the display of a selected plurality of linesof characters from said refresh memory in said display means, and saidmeans responsive including selection means for changing the selectedcontiguous lines from said refresh memory which are displayed in saiddisplay means.

2. The video display terminal of claim 1 wherein said refresh memorycomprises a recirculating register.

3. The video display terminal of claim 2 wherein said recirculatingregister is connected by a return loop, said return loop having meansfor shortening and lengthening the recirculation path so that charactersin said refresh memory can be inserted and deleted.

4. The video display terminal of claim 1 wherein control characters areprovided in said refresh memory for indicating the end of a line of dataso that all of said characters in said refresh memory are sequentiallystored in said refresh memory.

5. The video display terminal of claim 4 wherein control characters areprovided in said video display terminal for defining the start of thecharacters stored in the refresh memory, the start of the displayportion of the characters stored in said refresh memory and the end ofthe characters stored in said refresh memory.

6. The video display terminal of claim 5 wherein said terminal includescontrol means for removing said character representative of the start ofthe characters to be displayed from one position and returning it toanother position within said refresh memory.

7. The video display terminal of claim 6 wherein said control meanscomprises means for recognizing said start of display character when itis positioned in a predetermined portion of said recirculation path,means responsive to said control means for shortening the recirculationpath whensaid start of display character is determined, maintaining saidshortened path until such time as the desired position in said refreshmemory for said start of display character is located in saidrecirculation path and lengthening said recirculation path at thedesired position for insertion of said start of display character.

8. The video display terminal of claim 6 wherein said control meansfurther include counting means for counting the number of end of linecharacters that pass through said recirculation path, said countingmeans including a pair of counters, the first of said counters beingmaintained at a count which enables the start of display character to beplaced one line earlier in said refresh memory and a second counterbeing maintained at a count to enable the determination of the place entf the tart of displa c aracter a p redet rme num rof mes 1n sai re resmemory romt e control character for the end of the characters in thedisplay memory.

9. The video display terminal of claim 1 wherein said terminal furtherincludes a line bufier register, said line buffer register beingutilized to address the character generator for displaying a line ofcharacters on the display means.

10. In a video display terminal, a recirculating register having avariable length recirculation path, said recirculating register havingstored therein the coded representation of a plurality of datacharacters and control characters, said control characters including afirst character which indicates that each of said data characters in apredetermined plurality of rows of 7 characters immediately followingsaid first character are to be displayed, means responsive to saidrecirculation path for determining the presence of said first charactertherein, said means responsive including means for shortening saidrecirculation path to remove said first character and means forrestoring the length of said recirculation path to reinsert said firstcharacter in a different portion of said recirculating register withrespect to the data characters and control characters stored therein.

1. In a video display terminal having a refresh memory, a charactergenerator and a display means wherein said refresh memory is utilized toenable said character generator to provide signals to said display meansfor displaying characters, the codes of which are stored in said refreshmemory, said refresh memory having stored therein a plurality ofcontiguous lines of characters larger than the number of lines which canbe simultaneously displayed on said display, means responsive to saidrefresh memory for enabling the display of a selected plurality of linesof characters from said refresh memory in said display means, and saidmeans responsive including selection means for changing the selectedcontiguous lines from said refresh memory which are displayed in saiddisplay means.
 2. The video display terminal of claim 1 wherein saidrefresh memory comprises a recirculating register.
 3. The video displayterminal of claim 2 wherein said recirculating register is connected bya return loop, said return loop having means for shortening andlengthening the recirculation path so that characters in said refreshmemory can be inserted and deleted.
 4. The video display terminal ofclaim 1 wherein control characters are provided in said refresh memoryfor indicating the end of a line of data so that all of said charactersin said refresh memory are sequentially stored in said refresh memory.5. The video display terminal of claim 4 wherein control characters areprovided in said video display terminal for defining the start of thecharacters stored in the refresh memory, the start of the displayportion of the characters stored in said refresh memory and the end ofthe characters stored in said refresh memory.
 6. The video displayterminal of claim 5 wherein said terminal includes control means forremoving said character representative of the start of the characters tobe displayed from one position and returning it to another positionwithiN said refresh memory.
 7. The video display terminal of claim 6wherein said control means comprises means for recognizing said start ofdisplay character when it is positioned in a predetermined portion ofsaid recirculation path, means responsive to said control means forshortening the recirculation path when said start of display characteris determined, maintaining said shortened path until such time as thedesired position in said refresh memory for said start of displaycharacter is located in said recirculation path and lengthening saidrecirculation path at the desired position for insertion of said startof display character.
 8. The video display terminal of claim 6 whereinsaid control means further include counting means for counting thenumber of end of line characters that pass through said recirculationpath, said counting means including a pair of counters, the first ofsaid counters being maintained at a count which enables the start ofdisplay character to be placed one line earlier in said refresh memoryand a second counter being maintained at a count to enable thedetermination of the placement of the start of display character apredetermined number of lines in said refresh memory from the controlcharacter for the end of the characters in the display memory.
 9. Thevideo display terminal of claim 1 wherein said terminal further includesa line buffer register, said line buffer register being utilized toaddress the character generator for displaying a line of characters onthe display means.
 10. In a video display terminal, a recirculatingregister having a variable length recirculation path, said recirculatingregister having stored therein the coded representation of a pluralityof data characters and control characters, said control charactersincluding a first character which indicates that each of said datacharacters in a predetermined plurality of rows of charactersimmediately following said first character are to be displayed, meansresponsive to said recirculation path for determining the presence ofsaid first character therein, said means responsive including means forshortening said recirculation path to remove said first character andmeans for restoring the length of said recirculation path to reinsertsaid first character in a different portion of said recirculatingregister with respect to the data characters and control charactersstored therein.